钟控型触发器的VHDL描述

同步清零

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY Dchu IS

PORT (CLK,D:IN STD_LOGIC;

Q:OUT STD_LOGIC;

SCLK:IN STD_LOGIC);

END;

ARCHITECTURE FFQ OF Dchu IS SIGNAL Q1:STD_LOGIC;

BEGIN

PROCESS (SCLK,CLK,Q1)

BEGIN

IF CLK'EVENT AND CLK='1' THEN

IF SCLK='1' THEN

Q1<='0';

ELSE Q1<=D;

END IF;

END IF;

END PROCESS;

Q<=Q1; END FFQ;

异步置位

apre LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY Dchu IS PORT ( CLK : IN STD_LOGIC;

D : IN STD_LOGIC;

Q :OUT STD_LOGIC;

APRE :IN STD_LOGIC

); E

ND;

ARCHITECTURE FFQ OF Dchu IS SIGNAL

Q1:STD_LOGIC;

BEGIN PROCESS (APRE,CLK,Q1)

BEGIN IF APRE='1'

THEN Q1<='1';

ELSIF CLK'EVENT AND CLK='1'

THEN Q1<=D;

END IF;

END PROCESS;

Q<=Q1; END FFQ;